Semiconductor structure and manufacturing method thereof
US10340350B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2018 |
| Grant date | Jul 2, 2019 |
| Priority date | — |
| Expiry date | Jul 25, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0193
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.