Dishing prevention dummy structures for semiconductor devices
US10340357B2 · kind B2 · utility
7Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2018 |
| Grant date | Jul 2, 2019 |
| Priority date | — |
| Expiry date | Apr 27, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0151
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.