Gate structure with dual width electrode layer
US10340359B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 6, 2018 |
| Grant date | Jul 2, 2019 |
| Priority date | — |
| Expiry date | Feb 6, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32139
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A high-k dielectric metal gate (HKMG) transistor includes a substrate, an HKMG gate stack with a gate dielectric layer and a gate electrode layer positioned above the substrate. The gate electrode layer has an upper portion and a lower portion. A first liner contacts a sidewall portion of the upper portion. A spacer contacts the first liner and a sidewall portion of the lower portion. Raised source and drain regions are positioned adjacent the spacer. A height of the uppermost surface of the spacer is greater than a height of an uppermost surface of the raised source and drain regions. A width of the upper portion between the raised source and drain regions is smaller than a width of the lower portion between the raised source and drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.