Patent · US Active

Forming of a MOS transistor based on a two-dimensional semiconductor material

US10340361B2 · kind B2 · utility

1Cited by

1References

9Claims

0Family size

Assignee

COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

Fabrice Nemouchi · Moirans, FR
Yves Morand · Grenoble, FR

Key dates

Filing date	May 17, 2018
Grant date	Jul 2, 2019
Priority date	—
Expiry date	May 17, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH10D62/882
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A MOS transistor manufacturing method, including: forming a first conductive or semiconductor layer; forming a sacrificial gate on the first layer and a second layer made of an insulating material laterally surrounding the sacrificial gate; forming, on either side of the sacrificial gate, source and drain electric connection elements crossing the second layer and contacting the first layer; removing the sacrificial gate and the portion of the first layer located vertically in line with the sacrificial gate; depositing a third layer made of a two-dimensional semiconductor material; depositing a fourth layer made of an insulating material on the third layer; and forming a conductive gate in the opening, on the fourth layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.