Inventor · Grenoble, FR

Yves Morand

50Patents
6h-index
51Co-inventors
75Inventor score

Filing activity: Dec 29, 1998 → Apr 22, 2020

Most-cited inventions

PatentTitleAreaCited byStatus
US8470689B2 Method for forming a multilayer structure Performing Operations; Transporting 197 Active
US7598145B2 Method for producing Si1-yGey based zones with different contents in Ge on a same substrate by condensation of germanium Electricity 49 Active
US6521533B1 Method for producing a copper connection Electricity 16 Expired
US7041539B2 Method for making an island of material confined between electrodes, and application to transistors Emerging Cross-Sectional Technologies 15 Expired
US9117805B2 Air-spacer MOS transistor Electricity 12 Active
US7829916B2 Transistor with a germanium-based channel encased by a gate electrode and method for producing one such transistor Electricity 10 Active
US6875686B2 Method for fabricating a structure of interconnections comprising an electric insulation including air or vacuum gaps Electricity 6 Expired
US7141837B2 High-density MOS transistor Electricity 6 Expired
US9502558B2 Local strain generation in an SOI substrate Electricity 4 Active
US7129563B2 Method of fabricating a semiconductor device comprising a gate dielectric made of high dielectric permittivity material Electricity 4 Expired
US6734483B2 Process for fabricating a capacitor within an integrated circuit, and corresponding integrated circuit Electricity 3 Expired
US9269570B2 Contact on a heterogeneous semiconductor substrate Electricity 3 Active
US7361592B2 Method for producing a component comprising at least one germanium-based element and component obtained by such a method Electricity 3 Active
US9899217B2 Method for producing a strained semiconductor on insulator substrate Electricity 2 Active
US8962399B2 Method of making a semiconductor layer having at least two different thicknesses Electricity 2 Active
US9935019B2 Method of fabricating a transistor channel structure with uniaxial strain Electricity 2 Active
US10014183B2 Method for patterning a thin film Electricity 2 Active
US6228765A Structure and method for forming conductive members in an integrated circuit Electricity 2 Expired
US9425051B2 Method for producing a silicon-germanium film with variable germanium content Electricity 2 Active
US7972971B2 Method for producing Si1-yGey based zones with different contents in Ge on a same substrate by condensation of germanium Electricity 2 Active
US9536951B2 FinFET transistor comprising portions of SiGe with a crystal orientation [111] Electricity 1 Active
US9711567B2 Process for fabricating an integrated circuit cointegrating a FET transistor and an OxRAM memory location Electricity 1 Active
US9276073B2 Nanowire and planar transistors co-integrated on utbox SOI substrate Emerging Cross-Sectional Technologies 1 Active
US8722471B2 Method for forming a via contacting several levels of semiconductor layers Electricity 1 Active
US7625811B2 Method for producing distinct first and second active semi-conducting zones and use thereof for fabricating C-MOS structures Electricity 1 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.