Clock generating circuit and method of operating the same
US10340897B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2018 |
| Grant date | Jul 2, 2019 |
| Priority date | — |
| Expiry date | Jul 19, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock circuit includes a first latch, second latch, first trigger circuit and clock trigger circuit. The first latch generates a first latch output signal based on a first control signal, an enable signal and an output clock signal. The second latch is coupled to the first latch, and configured to generate the output clock signal responsive to a second control signal. The first trigger circuit is coupled to the first latch and the second latch, and configured to adjust the output clock signal responsive to at least the first latch output signal or a reset signal. The clock trigger circuit is coupled to the first latch and the first trigger circuit by a first node, is configured to generate the first control signal responsive to an input clock signal, and configured to control the first latch and the first trigger circuit based on at least the first control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.