Patent · US Active

Mechanism to provide workload and configuration-aware deterministic performance for microprocessors

US10345884B2 · kind B2 · utility

0Cited by
12References
20Claims
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Key dates

Filing dateAug 16, 2016
Grant dateJul 9, 2019
Priority date
Expiry dateDec 3, 2036

Classification

  • Technology area (CPC Y)Emerging Cross-Sectional Technologies
  • CPC primaryY02D10/00
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.