Method and apparatus for per-deck erase verify and dynamic inhibit in 3d NAND
US10346088B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2017 |
| Grant date | Jul 9, 2019 |
| Priority date | — |
| Expiry date | Sep 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an apparatus comprises a controller to determine an erase state of a first memory deck independently from an erase state of a second memory deck, the first memory deck comprising a first plurality of wordlines and a first channel, the first memory deck comprising a first plurality of memory cells that are each coupled to the first channel and a respective one of the first plurality of wordlines; the second memory deck comprising a second plurality of wordlines and a second channel, the second channel coupled to the first channel, the second memory deck comprising a second plurality of memory cells that are each coupled to the second channel and a respective one of the second plurality of wordlines; and determine an erase state of the second memory deck independently from an erase state of the first memory deck.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.