Giuseppina Puzzilli
36Patents
5h-index
34Co-inventors
65Inventor score
Filing activity: Sep 10, 2009 → Oct 21, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8228735B2 | Memory array having memory cells coupled between a programmable drain select gate and a non-programmable source select gate | Physics | 15 | Active |
| US8619474B2 | Data line management in a memory device | Physics | 11 | Active |
| US10346088B2 | Method and apparatus for per-deck erase verify and dynamic inhibit in 3d NAND | Electricity | 8 | Active |
| US8514624B2 | In-field block retiring | Physics | 7 | Active |
| US8767467B2 | In-field block retiring | Physics | 5 | Active |
| US8369158B2 | Erase operations and apparatus for a memory device | Physics | 2 | Active |
| US11461035B2 | Adjusting a preprogram voltage based on use of a memory device | Physics | 2 | Active |
| US11360700B2 | Partitions within snapshot memory for buffer and snapshot memory | Physics | 1 | Active |
| US11301346B2 | Separate trims for buffer and snapshot | Emerging Cross-Sectional Technologies | 1 | Active |
| US11443812B2 | Setting an initial erase voltage using feedback from previous operations | Physics | 1 | Active |
| US11385819B2 | Separate partition for buffer and snapshot memory | Physics | 1 | Active |
| US11709616B2 | Adjusting a preprogram voltage based on use of a memory device | Physics | 1 | Active |
| US11288160B2 | Threshold voltage distribution adjustment for buffer | Physics | 1 | Active |
| US11899966B2 | Implementing fault tolerant page stripes on low density memory systems | Physics | 0 | Active |
| US11776629B2 | Threshold voltage based on program/erase cycles | Physics | 0 | Active |
| US11468949B2 | Temperature-dependent operations in a memory device | Physics | 0 | Active |
| US11189355B1 | Read window based on program/erase cycles | Physics | 0 | Active |
| US11430528B2 | Determining a read voltage based on a change in a read window | Physics | 0 | Active |
| US9490025B2 | Methods of programming memory devices | Physics | 0 | Active |
| US11694763B2 | Read voltage calibration for copyback operation | Physics | 0 | Active |
| US11449271B2 | Implementing fault tolerant page stripes on low density memory systems | Physics | 0 | Active |
| US11487436B2 | Trims corresponding to logical unit quantity | Physics | 0 | Active |
| US12026052B2 | Partitioned memory having error detection capability | Physics | 0 | Active |
| US11847335B2 | Latent read disturb mitigation in memory devices | Physics | 0 | Active |
| US11797216B2 | Read calibration based on ranges of program/erase cycles | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.