Checking wafer-level integrated designs for rule compliance
US10346580B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2016 |
| Grant date | Jul 9, 2019 |
| Priority date | — |
| Expiry date | Sep 13, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for checking a wafer-level design for compliance with a rule include determining whether each chip layout out of multiple chip layouts complies internally with one or more layout design rules. A tile area is determined, having a size that is based on the one or more layout design rules, that crosses a boundary between adjacent chip layouts and that leaves at least a portion of each chip layout uncovered. It is determined whether portions of the plurality of chip layouts inside the tile area comply with the one or more layout design rules. The chip layouts are modified, if chip layout area within the tile area fails to comply with the design rule, to bring non-compliant periphery chip regions into compliance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.