Interconnect formation process using wire trench etch prior to via etch, and related interconnect
US10347528B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2018 |
| Grant date | Jul 9, 2019 |
| Priority date | — |
| Expiry date | Mar 6, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1063
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming an interconnect of an IC are disclosed. The methods etch a wire trench opening partially into an ILD layer using a hard mask, and form a metal liner sidewall spacer on sidewalls of the wire trench opening, prior to etching via openings that create a via-wire opening with the wire trench opening. The metal liner sidewall spacer protects against chamfering during the via etch and/or removal of an etch stop layer over conductive structures in an underlying ILD layer. In one embodiment, a barrier liner is deposited over the metal liner sidewall spacer, creating a double layered sidewall spacer on the sidewalls of the wire trench opening portion of the via-wire opening. A conductor is deposited to form a unitary via-wire conductive structure. An interconnect includes the double layered sidewall spacer on the sidewalls of a wire trench opening portion of the via-wire conductive structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.