Semiconductor packages having redistribution substrate
US10347611B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2017 |
| Grant date | Jul 9, 2019 |
| Priority date | — |
| Expiry date | Jan 16, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/117
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package is provided which includes a redistribution substrate, an interconnect substrate on the redistribution substrate, a metal layer on the semiconductor chip, a semiconductor chip on the redistribution substrate and in the hole of the interconnect substrate, and a mold layer in a gap between the semiconductor chip and the interconnect substrate. The interconnect substrate includes a hole penetrating thereinside. The interconnect substrate includes base layers and a conductive member extending through the base layers. A top surface of the interconnect substrate is positioned either above or below the level of the top surface of the metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.