Fabrication methods of forming cylindrical vertical SI etched channel 3D switching devices
US10347822B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2017 |
| Grant date | Jul 9, 2019 |
| Priority date | — |
| Expiry date | Dec 28, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/10
Abstract
A method of forming a cylindrical vertical transistor; the method, according to one embodiment, includes: forming a cylindrical pillar from a single block of silicon, forming an oxide layer over an exterior of the cylindrical pillar and exposed surfaces of the block of silicon, coating the oxide layer with a spin-on-glass (SOG), depositing a source mask over a majority of the SOG coating, and removing a portion of the SOG coating and underlying oxide layer, where the portion removed is defined by the source mask. Other systems and methods are also described in additional embodiments herein which provide various different improved processes of forming the cylindrical gate contacts, the source contacts, and/or the drain contacts for vertical transistor structures which also include the aforementioned cylindrical pillar channel structures and cylindrical gate in comparison to conventional surface transistor structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.