Method for fabricating a damascene self-aligned ferroelectric random access memory (F-RAM) device structure employing reduced processing steps
US10347829B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2013 |
| Grant date | Jul 9, 2019 |
| Priority date | — |
| Expiry date | Oct 17, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/689
Abstract
A method for fabricating a non-volatile, ferroelectric random access memory (F-RAM) device with a reduced number of masking and etching steps is described. In one embodiment, the method includes forming an opening in an insulating layer over a surface of a substrate to expose a portion of the surface, and forming first spacers on sidewalls of the opening. A conductive layer is formed on the portion of the surface exposed in the opening and separated from the first spacers on the sidewalls of the opening by a gap therebetween. A bottom electrode of a ferroelectric capacitor is formed over the conductive layer and in the gap laterally of the conductive layer, a ferroelectric dielectric formed on the bottom electrode between the first spacers, and a top electrode formed on the ferroelectric dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.