Optimizing an integrated circuit (IC) design comprising at least one wide-gate or wide-bus
US10354032B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2016 |
| Grant date | Jul 16, 2019 |
| Priority date | — |
| Expiry date | Mar 14, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and techniques are described for optimizing an integrated circuit (IC) design. Some embodiment can perform enumeration on a hardware description language (HDL) description of an IC design to obtain a enumerated IC design that includes at least one technology-independent wide-gate or technology-independent wide-bus, wherein the technology-independent wide-gate represents a logical function that is performed on a variable number of inputs, and wherein the technology-independent wide-bus represents a variable number of signals that are part of a bus. The embodiments can then perform technology-independent IC optimization, synthesis, and technology-dependent IC optimization to obtain an optimized and synthesized IC design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.