Reduced shifter memory system
US10354717B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2018 |
| Grant date | Jul 16, 2019 |
| Priority date | — |
| Expiry date | May 10, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1078
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the present disclosure eliminating the need for a memory device to have both a shifter that shifts input pin values from an input domain into a parity domain and another shifter that shifts a decoded command from the input domain into the parity domain. A memory device can achieve this by, when parity is being performed, shifting the input from the input pins into the parity domain prior to decoding the command. Using a multiplexer, the decoder can receive the command pin portion of the shifted input when parity checking is being performed and can receive the un-shifted command pin input when parity checking is not being performed. The decoder can use the command pin portion of the shifted input to generate shifted and decoded commands or can use the un-shifted command pin input to generate decoded commands.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.