Methods and apparatus for programming barrier modulated memory cells
US10354724B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2017 |
| Grant date | Jul 16, 2019 |
| Priority date | — |
| Expiry date | Sep 15, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/77
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device is provided that includes a memory controller coupled to a memory array. The memory controller is adapted to perform a closed loop training interval and perform an open loop programming interval. The closed loop training interval determines a corresponding first state successful voltage and a corresponding second state successful voltage for a first group of memory cells each including a barrier modulated switching structure. The open loop programming interval programs a second group of memory cells each including a barrier modulated switching structure to a first state and a second state using the corresponding first state successful voltage and the corresponding second state successful voltage, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.