Electronic package and method for fabricating the same
US10354891B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2018 |
| Grant date | Jul 16, 2019 |
| Priority date | — |
| Expiry date | Apr 4, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic package and a method for fabricating the same are provided. The method includes forming a filling material, such as an underfill, between a carrier and a plurality of electronic components and filling the filling material in a space between the electronic components to form a spacing portion. The spacing portion has a first segment and a second segment separated from each other to serve as a stress buffer zone. Therefore, when an encapsulation layer encapsulating the electronic components is subsequently ground, the present disclosure can effectively prevent the electronic components from being cracked due to stresses induced by the external grinding force.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.