Integrated circuit with improved resistive region
US10354926B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 3, 2017 |
| Grant date | Jul 16, 2019 |
| Priority date | — |
| Expiry date | Oct 3, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/209
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.