Graphene as interlayer dielectric
US10354955B2 · kind B2 · utility
1Cited by
3References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2017 |
| Grant date | Jul 16, 2019 |
| Priority date | — |
| Expiry date | Nov 7, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit may include multiple back-end-of-line (BEOL) interconnect layers. The BEOL interconnect layers may include conductive lines and conductive vias. The integrated circuit may further include an interlayer dielectric (ILD) between the BEOL interconnect layers. The ILD may include the conductive lines and the conductive vias. At least a portion of the ILD may include a low-K insulating graphene alloy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.