Memory cells, methods of forming an array of two transistor-one capacitor memory cells, and methods used in fabricating integrated circuitry
US10355002B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 2, 2017 |
| Grant date | Jul 16, 2019 |
| Priority date | — |
| Expiry date | Sep 7, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B53/30
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory cell comprises first and second transistors laterally displaced relative one another. A capacitor is above the first and second transistors. The capacitor comprises a container-shape conductive first capacitor node electrically coupled with a first current node of the first transistor, a conductive second capacitor node electrically coupled with a first current node of the second transistor, and a capacitor dielectric material between the first capacitor node and the second capacitor node. The capacitor dielectric material extends across a top of the container-shape first capacitor node. Additional embodiments and aspects, including method, are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.