Three dimensional perpendicular magnetic junction with thin-film transistor
US10355045B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2017 |
| Grant date | Jul 16, 2019 |
| Priority date | — |
| Expiry date | Dec 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/10
Abstract
According to one embodiment, an apparatus includes: a substrate, an array of 3D structures, where each 3D structure includes a source region having a first conductivity, a series of layers positioned in a vertical direction, a channel material on a surface of at least one sidewall of each 3D structure, and a gate dielectric material on the channel material. The series of layers includes a dielectric layer positioned above the substrate, a plurality of a set of MTJ layers positioned above the dielectric layer, and a buffer layer positioned in between the dielectric layer and each set of MTJ layers thereof. The magnetic memory device further includes an isolation region positioned between the 3D structures and at least one gate region positioned above the isolation region, where each gate region is coupled to at least one sidewall of each 3D structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.