Fabrication methods of forming annular vertical SI etched channel MOS devices
US10355047B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2017 |
| Grant date | Jul 16, 2019 |
| Priority date | — |
| Expiry date | Dec 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
Abstract
A method, according to one embodiment, includes: forming an annular cylindrical channel from a single block of electrically conductive material; forming an oxide layer over exposed surfaces of the annular cylindrical channel and exposed surfaces of the block of electrically conductive material; removing a portion of the oxide layer from an exterior base of the annular cylindrical channel, thereby forming a source contact recess which surrounds the base of the annular cylindrical channel; ion-implanting the exposed electrically conductive material substrate at a base of the source contact recess; and depositing a silicide material in the source contact recess, thereby forming a source contact tab. Moreover, other systems and methods are also described in additional embodiments herein which provide various different improved processes of forming the annular cylindrical channels, the source contact tabs, and/or the cylindrical pillar gate contacts for vertical transistor structures in comparison to conventional surface transistor structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.