Methods and apparatus for three-dimensional non-volatile memory
US10355049B1 · kind B1 · utility
3Cited by
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21Claims
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Key dates
| Filing date | Jun 28, 2018 |
| Grant date | Jul 16, 2019 |
| Priority date | — |
| Expiry date | Jun 28, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/823
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is provided that includes a bit line above a substrate, a word line above the substrate, and a non-volatile memory cell between the bit line and the word line. The non-volatile memory cell includes a reversible resistance-switching memory element coupled in series with an isolation element. The isolation element includes a first selector element coupled in series with a second selector element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.