Memory devices and electronic systems having a hybrid cache including static and dynamic caches with single and multiple bits per cell, and related methods
US10359933B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2016 |
| Grant date | Jul 23, 2019 |
| Priority date | — |
| Expiry date | Sep 19, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7206
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory having a memory controller is configured to operate a hybrid cache including a dynamic cache including x-level cell (XLC) (e.g., multi-level cell (MLC)) blocks and a static cache including single level cell (SLC) blocks. A method of operating the memory includes storing at least a portion of host data into the SLC blocks as static cache; and storing at least another portion of host data into XLC blocks in an SLC mode as dynamic cache responsive to a burst of host data being determined to be greater than the static cache can handle. At least one of the static cache or dynamic cache may be disabled based on monitoring a workload of the hybrid cache relative to a Total Bytes Written (TBW) specification, such as by counting program-erase (PE) cycles of different portions of memory, or responsive to the workload exceeding a predetermined threshold defining one or more switch points.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.