Integrated metal layer aware optimization of integrated circuit designs
US10360341B2 · kind B2 · utility
3Cited by
9References
20Claims
0Family size
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Key dates
| Filing date | Aug 31, 2017 |
| Grant date | Jul 23, 2019 |
| Priority date | — |
| Expiry date | Dec 19, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and techniques are described for optimizing an integrated circuit (IC) design. Before routing is performed on the IC design in an IC design flow, an IC design tool can iteratively perform a set of operations, the set of operations comprising: (1) modifying a net in the IC design to obtain a modified net, (2) determining a metal layer for routing the modified net, (3) computing a resistance value and a capacitance value of the modified net based on the metal layer, and (4) computing a delay value for the modified net based on the resistance value and the capacitance value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.