Substrate construction and electronic package including the same
US10361150B2 · kind B2 · utility
4Cited by
0References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 9, 2017 |
| Grant date | Jul 23, 2019 |
| Priority date | — |
| Expiry date | May 9, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The disclosure provides a substrate construction applicable to a 3D package, including a silicon substrate for carrying a chip on an upper side thereof, and a circuit structure formed underneath the silicon substrate for being connected to solder balls via conductive pads of the circuit structure, thereby obtaining the same specification of the conductive pads as ball-planting pads of conventional package substrates and avoiding the manufacturing and use of conventional package substrates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.