Semiconductor memory device
US10365325B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 22, 2017 |
| Grant date | Jul 30, 2019 |
| Priority date | — |
| Expiry date | Sep 14, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for memory I/O tests using integrated test data paths are provided. In an example, a method for operating input/output data paths of a memory apparatus can include receiving, during a first mode, non-test information at a data terminal of a first channel of the memory apparatus from a memory array of the first channel via a first data path, receiving during a first test mode, first test information at the data terminal of the first channel from a first additional data path coupling the first channel with a second channel of the memory apparatus, and wherein an interface die of the memory apparatus includes the first data path and the additional data path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.