Manufacturing method of semiconductor package
US10366907B2 · kind B2 · utility
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2Claims
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Key dates
| Filing date | Jun 27, 2018 |
| Grant date | Jul 30, 2019 |
| Priority date | — |
| Expiry date | Jun 27, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1815
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is provided a manufacturing method of a semiconductor package in which plural semiconductor chips different in the thickness are mounted. In the manufacturing method, the back surface of a package board in which the plural semiconductor chips on a wiring base are collectively sealed by a sealant is held by a holding tape and a resin layer is thinned by a shaping abrasive stone. Then, a dividing unit is caused to cut to the middle of the holding tape along planned dividing lines to divide the package board into individual semiconductor packages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.