Vertical semiconductor devices and methods of manufacturing the same
US10367002B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 2016 |
| Grant date | Jul 30, 2019 |
| Priority date | — |
| Expiry date | Oct 24, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/63
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.