Semiconductor memory device

US10367054B2 · kind B2 · utility

Assignee

• TOSHIBA MEMORY CORPORATION · JP

Inventors

• Hidenori Miyagawa · Yokohama, JP
• Riichiro Takaishi · Kawasaki, JP
• Toshinori Numata · Kamakura, JP

Key dates

• Filing date: Sep 8, 2017
• Grant date: Jul 30, 2019
• Expiry date: Sep 8, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/50

Abstract

A semiconductor memory device according to an embodiment comprises a plurality of control gate electrodes, a first semiconductor layer, and a gate insulating layer. The plurality of control gate electrodes are arranged in a first direction that intersects a surface of a substrate. The first semiconductor layer extends in the first direction and faces side surfaces in a second direction intersecting the first direction, of the plurality of control gate electrodes. The gate insulating layer is provided between the control gate electrode and the first semiconductor layer. In addition, the first semiconductor layer includes: a first portion having a first plane orientation; and a second portion having a second plane orientation which is different from the first plane orientation.