Methods of forming backside self-aligned vias and structures formed thereby
US10367070B2 · kind B2 · utility
5Cited by
4References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2015 |
| Grant date | Jul 30, 2019 |
| Priority date | — |
| Expiry date | Sep 24, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and structures formed thereby are described, of forming self-aligned contact structures for microelectronic devices. An embodiment includes forming a trench in a source/drain region of a transistor device disposed in a device layer, wherein the device layer is on a substrate, forming a fill material in the trench, forming a source/drain material on the fill material, forming a first source/drain contact on a first side of the source/drain material, and then forming a second source drain contact on a second side of the source/drain material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.