Scrambling apparatus and method thereof
US10372948B2 · kind B2 · utility
1Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2015 |
| Grant date | Aug 6, 2019 |
| Priority date | — |
| Expiry date | Dec 28, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1052
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device is provided which comprises a memory array, a first scrambling circuit and a second scrambling circuit. The first scrambling circuit is configured to provide first scrambled data with a first scrambling pattern in response to input data. The second scrambling circuit is configured to provide second scrambled data with a second scrambling pattern in response to the first scrambled data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.