Semiconductor layered device with data bus
US10373657B2 · kind B2 · utility
39Cited by
3References
16Claims
0Family size
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Key dates
| Filing date | Aug 10, 2016 |
| Grant date | Aug 6, 2019 |
| Priority date | — |
| Expiry date | Jan 6, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first semiconductor chip and a second semiconductor chips that are stacked with each other via through substrate vias (TSVs) provided in one of the first semiconductor chip and the second semiconductor chip. The first semiconductor chip and the second semiconductor chips communicate with each other by use of data bus inversion data that have been encoded using a DBI algorithm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.