Logic layout with reduced area and method of making the same

US10373942B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Ram Asra · Malta, US
• Mohit Bajaj · Savanuru, IN
• Edward J. Nowak · South Burlington, US
• Kota V. R. M. Murali · Bengaluru, IN

Key dates

• Filing date: Dec 1, 2017
• Grant date: Aug 6, 2019
• Expiry date: Dec 1, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/215

Abstract

A method of forming a SRAM semiconductor device with reduced area layout and a resulting device are provided. Embodiments include forming a first field effect transistor (FET) over a substrate; forming an insulating material over the first FET; forming a second FET over the insulating material; and patterning the first FET, insulating material and second FET to form fins over the substrate.