Gated bipolar junction transistors, memory arrays, and methods of forming gated bipolar junction transistors
US10373956B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2015 |
| Grant date | Aug 6, 2019 |
| Priority date | — |
| Expiry date | Feb 4, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/711
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.