Structure and formation method of semiconductor device structure with nanowires
US10374059B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2017 |
| Grant date | Aug 6, 2019 |
| Priority date | — |
| Expiry date | Nov 12, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Structures and formation methods of a semiconductor device structure are provided. The method includes providing a substrate having a base portion and a fin portion over the base portion. The fin portion has a channel region and a source/drain region. The method also includes forming a stack structure over the fin portion. The stack structure includes first and second semiconductor layers. The method also includes forming a source/drain portion in the stack structure at the source/drain region, and removing a portion of the second semiconductor layer in the channel region in an etching process. The remaining portion of the first semiconductor layer in the channel region forms a nanowire. The method further includes forming a gate dielectric layer surrounding the nanowire, forming a high-k dielectric layer surrounding the gate dielectric layer, and forming a gate electrode surrounding the high-k dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.