Bit line control that reduces select gate transistor disturb in erase operations
US10381083B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2018 |
| Grant date | Aug 13, 2019 |
| Priority date | — |
| Expiry date | Jun 25, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation for memory cells in a string. During the erase operation, a channel potential gradient near the select gate transistors is reduced when the voltages of the bit line and the substrate are suitably controlled. In one approach, the voltage of the substrate at a source end of the memory string is increased to an intermediate level first before being increased to the erase voltage threshold level while the voltage of the bit line is held at a reference voltage level to delay floating the voltage of the bit line. Another approach builds off the first approach by temporarily decreasing the voltage of the bit line to a negative level before letting the voltage of the bit line to float at the same time as the voltage of the substrate is increased to the erase voltage threshold level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.