Integrated circuits with memory cell test circuits and methods for producing the same
US10381339B1 · kind B1 · utility
5Cited by
1References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2018 |
| Grant date | Aug 13, 2019 |
| Priority date | — |
| Expiry date | Mar 21, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a first and second dummy memory cell positioned within a dummy memory bank area. A first dummy top electrode overlies the first and second dummy memory cells, and is in electrical communication with the first and second dummy memory cells. A test circuit is in electrical communication with the first dummy top electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.