Method of forming MOS and bipolar transistors

US10381344B2 · kind B2 · utility

Assignees

• STMicroelectronics (Crolles 2) SAS · FR
• STMicroelectronics (Rousset) SAS · FR
• COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

• Olivier Weber · Grenoble, FR
• Emmanuel Richard · Chambéry, FR
• Philippe Boivin · Venelles, FR

Key dates

• Filing date: Feb 15, 2018
• Grant date: Aug 13, 2019
• Expiry date: Feb 15, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/8413

Abstract

Bipolar transistors and MOS transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer. On a side of the bipolar transistors: an insulating region including the insulating layer is formed; openings are etched through the insulating region to delimit insulating walls; the openings are filled with first epitaxial portions; and the first epitaxial portions and a first region extending under the first epitaxial portions and under the insulating walls are doped. On the side of the bipolar transistors and on a side of the MOS transistors: gate structures are formed; second epitaxial portions are made; and the second epitaxial portions covering the first epitaxial portions are doped.