Floating body memory cell having gates favoring different conductivity type regions
US10381350B2 · kind B2 · utility
3Cited by
16References
20Claims
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Key dates
| Filing date | Oct 3, 2018 |
| Grant date | Aug 13, 2019 |
| Priority date | — |
| Expiry date | Oct 3, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.