Method to fabricate discrete vertical transistors
US10381408B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2016 |
| Grant date | Aug 13, 2019 |
| Priority date | — |
| Expiry date | Mar 24, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/74
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure generally relates to the fabrication of metal-oxide-semiconductor (MOS) select transistors in a vertical orientation such that the transistor pair fits within the footprint of a 4F2 memory cell. The present disclosure further relates to the simultaneous fabrication of a vertical stack of transistors in which each transistor is distinct, as opposed to being serially connected in a NAND-like string. An initial stack of materials is built to include silicon layers to act as source and drain regions as well as to serve as epitaxial growth seed points. As such, the transistor disclosed may be utilized in conjunction with memory elements such as Phase Change, Resistive, or Magnetic RAM memory within array designs, among others.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.