Sequential test access port selection in a JTAG interface

US10386411B2 · kind B2 · utility

Assignee

• STMicroelectronics International N.V. · NL

Inventors

• Venkata Narayanan Srinivasan · Greater Noida, IN
• Manish Sharma · Sunnyvale, US

Key dates

• Filing date: Aug 23, 2017
• Grant date: Aug 20, 2019
• Expiry date: Oct 17, 2037

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318597
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A JTAG interface in an IC includes a test mode select (TMS) pin receiving a TMS signal, a testing test access port (TAP) having a TMS signal input, a debugging test access port (TAP) having a TMS signal and glue logic coupled to receive a first output from the testing TAP and a second output from the debugging TAP. A flip-flop receives input from the testing TAP and the debugging TAP through the glue logic. A first AND gate has output coupled to the TMS signal input of the debugging TAP, and receives input from an output of the flip-flop and the TMS signal. An inverter has an input coupled to receive input from the flip-flop. A second AND gate has output coupled to the TMS signal input of the testing TAP, and receives input from the TMS signal and output of the inverter.