Shared local memory tiling mechanism
US10387160B2 · kind B2 · utility
6Cited by
0References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2017 |
| Grant date | Aug 20, 2019 |
| Priority date | — |
| Expiry date | Jun 9, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/122
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An apparatus to facilitate memory tiling is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads via access to the memory and tiling logic to apply a tiling pattern to memory addresses for data stored in the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.