Methods and devices using PVD ruthenium
US10388532B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2017 |
| Grant date | Aug 20, 2019 |
| Priority date | — |
| Expiry date | Sep 28, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Ruthenium containing gate stacks and methods of forming ruthenium containing gate stacks are described. The ruthenium containing gate stack comprises a polysilicon layer on a substrate; a silicide layer on the polysilicon layer; a barrier layer on the silicide layer; a ruthenium layer on the barrier layer; and a spacer layer comprising a nitride on sides of the ruthenium layer, wherein the ruthenium layer comprises substantially no ruthenium nitride after formation of the spacer layer. Forming the ruthenium layer comprises sputtering the ruthenium in a krypton environment on a high current electrostatic chuck comprising a high resistivity ceramic material. The sputtered ruthenium layer is annealed at a temperature greater than or equal to about 500° C.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.