Process integration method to tune resistivity of nickel silicide
US10388533B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2018 |
| Grant date | Aug 20, 2019 |
| Priority date | — |
| Expiry date | May 24, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53271
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for depositing a low resistivity nickel silicide layer used in forming an interconnect and electronic devices formed using the methods are described herein. In one embodiment, a method for depositing a layer includes positioning a substrate on a substrate support in a processing chamber, the processing chamber having a nickel target and a silicon target disposed therein, the substrate facing portions of the nickel target and the silicon target each having an angle of between about 10 degrees and about 50 degrees from the target facing surface of the substrate, flowing a gas into the processing chamber, applying an RF power to the nickel target and concurrently applying a DC power to the silicon target, concurrently sputtering silicon and nickel from the silicon and nickel targets, respectively, and depositing a NixSi1-x layer on the substrate, where x is between about 0.01 and about 0.99.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.