Patent · US Active

Chamferless via structures

US10388565B2 · kind B2 · utility

1Cited by
10References
18Claims
0Family size

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Key dates

Filing dateMay 17, 2018
Grant dateAug 20, 2019
Priority date
Expiry dateMay 17, 2038

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L23/528
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one non-self-aligned via within at least dielectric material; plugging the at least one non-self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one non-self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one non-self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.