Integrated circuit device with layered trench conductors
US10388664B2 · kind B2 · utility
4Cited by
10References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2018 |
| Grant date | Aug 20, 2019 |
| Priority date | — |
| Expiry date | Mar 6, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/562
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a multilayer stack, and a plurality of layered conductors extending in the multilayer stack and into a conductor layer beneath the multilayer stack. The layered conductor has a bottom conductor layer in ohmic electrical contact with the conductive layer in a substrate, an intermediate conductive liner layer over the bottom conductor layer and lining a portion of sidewall of the corresponding trench, and a top conductor layer on the top conductive liner layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.