Ta-Hung Yang
27Patents
4h-index
58Co-inventors
66Inventor score
Filing activity: Jul 13, 1995 → Feb 27, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5883001A | Integrated circuit passivation process and structure | Emerging Cross-Sectional Technologies | 33 | Expired |
| US9236219B2 | Measurement of line-edge-roughness and line-width-roughness on pre-layered structures | Electricity | 20 | Active |
| US7939451B2 | Method for fabricating a pattern | Electricity | 7 | Active |
| US6799152B1 | Critical dimension statistical process control in semiconductor fabrication | Physics | 5 | Expired |
| US10388664B2 | Integrated circuit device with layered trench conductors | Electricity | 4 | Active |
| US6875659B2 | Methods of code programming a mask ROM | Electricity | 4 | Expired |
| US6864185B2 | Fine line printing by trimming the sidewalls of pre-developed resist image | Physics | 3 | Expired |
| US9905509B2 | Inverted-T shaped via for reducing adverse stress-migration effects | Electricity | 3 | Active |
| US6969642B2 | Method of controlling implantation dosages during coding of read-only memory devices | Electricity | 2 | Expired |
| US6821684B2 | Method for fabricating mask ROM with self-aligned coding | Electricity | 1 | Expired |
| US7648921B2 | Method of forming dielectric layer | Electricity | 1 | Active |
| US10892265B2 | Word line structure and method of manufacturing the same | Electricity | 0 | Active |
| US8072577B2 | Lithography systems and processes | Physics | 0 | Active |
| US8653592B2 | Isolation structure, non-volatile memory having the same, and method of fabricating the same | Electricity | 0 | Active |
| US7632616B2 | Controlling system and method for operating the same | Electricity | 0 | Active |
| US8520194B2 | Method of forming a deposited material by utilizing a multi-step deposition/etch/deposition (D/E/D) process | Physics | 0 | Active |
| US10497652B1 | Semiconductor substrate and semiconductor device | Electricity | 0 | Active |
| US8034691B2 | HDP-CVD process, filling-in process utilizing HDP-CVD, and HDP-CVD system | Electricity | 0 | Active |
| US8085390B2 | Multivariate monitoring method for plasma process machine | Electricity | 0 | Active |
| US8519541B2 | Semiconductor device having plural conductive layers disposed within dielectric layer | Electricity | 0 | Active |
| US7846835B2 | Contact barrier layer deposition process | Electricity | 0 | Active |
| US8184288B2 | Method of depositing a silicon-containing material by utilizing a multi-step fill-in process in a deposition machine | Physics | 0 | Active |
| US7625819B2 | Interconnection process | Electricity | 0 | Active |
| US9252153B1 | Method of word-line formation by semi-damascene process with thin protective conductor layer | Electricity | 0 | Active |
| US7960835B2 | Fabrication of metal film stacks having improved bottom critical dimension | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.