Method and device for forming cut-metal-gate feature
US10388771B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2018 |
| Grant date | Aug 20, 2019 |
| Priority date | — |
| Expiry date | Jun 28, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0135
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A mask layer is formed over a semiconductor device. The semiconductor device includes: a gate structure, a first layer disposed over the gate structure, and an interlayer dielectric (ILD) disposed on sidewalls of the first layer. The mask layer includes an opening that exposes a portion of the first layer and a portion of the ILD. A first etching process is performed to etch the opening partially into the first layer and partially into the ILD. A liner layer is formed in the opening after the first etching process has been performed. A second etching process is performed after the liner layer has been formed. The second etching process extends the opening downwardly through the first layer and through the gate structure. The opening is filled with a second layer after the second etching process has been performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.